Meeting 1
Dates and location
Meeting 1 of the CATS project took place from April 22nd to April 26th, 2013 in Hồ Chí Minh City University of Technology, Việt Nam.
Participants
- Étienne André (LIPN, Université Paris 13, Sorbonne Paris Cité, France)
- Lin Shang-Wei (林尚威) (Temasek Labs, National University of Singapore)
- Liu Yang (刘杨) (Nanyang Technological University, Singapore)
- Nguyễn Truong Khanh (School of Computing, National University of Singapore)
- Laure Petrucci (LIPN, Université Paris 13, Sorbonne Paris Cité, France)
- Quản Thành Thơ (Department of Software Engineering, Hồ Chí Minh City University of Technology, Việt Nam)
- Thang Hoai Bui (Faculty of Computer Science and Engineering, Hồ Chí Minh City University of Technology, Việt Nam)
- …and various students
Talks: Monday
Nguyễn Hữu Vũ: AndroidCompiler
Mai Phuong Nam: LTL3BA
slides about implementation of LTL3BA in PAT, slides about fast LTL to Bũchi Automata (LTL2BA) and LTL3BA (upgrade from LTL2BA)
Talks: Tuesday
Nguyễn Minh Hai: Combine Static Analysis and Dynamic Testing to analyze Binary Code
Nguyễn Thien Binh
Coming soon
Dr. Thang Hoai Bui: Asynchronous Circuit Verification from Specification to Circuit
Laure Petrucci: Modular state spaces for prioritised Petri nets
Presentation of the following paper: C. Lakos and L. Petrucci. Modular state spaces for prioritised Petri nets. In Proc. of the Monterey Workshop, Redmond, WA, USA, april 2010, Volume 6662 of Lecture Notes in Computer Science, Springer Verlag. [PDF (author) | slides]
Étienne André: A Counterexample‐Based Incremental and Modular Verification Approach
Presentation of the following paper: Étienne André, Kaïs Klaï, Hanen Ochi and Laure Petrucci. A Counterexample‐Based Incremental and Modular Verification Approach. In Radu Calinescu and David Garlan (eds.), Monterey’12, LNCS 7539, Springer, pages 283–302, August 2012. [PDF | PDF (author version) | Slides | BibTeX]
Lin Shang-Wei: Automatic Compositional Verification of Timed Systems
Pictures
