| Authors |
Title |
How published |
C |
M |
PN |
RT |
Sec |
PS |
TA |
| Étienne André, Laurent Fribourg |
Behavioral Cartography of Timed Automata |
RP 2010, 2010 |
|
|
|
RT |
|
PS |
TA |
| Étienne André, Kaïs Klaï, Hanen Ochi and Laure Petrucci |
A Counterexample‐Based Incremental and Modular Verification Approach |
Monterey 2012, 2012 |
|
M |
|
|
|
|
|
| Shang-Wei Lin, Étienne André, Jing Song Dong, Jun Sun, and Yang Liu |
An Efficient Algorithm for Learning Event-Recording Automata |
ATVA 2011, 2011 |
C |
|
|
RT |
|
|
TA |
| Shang-Wei Lin, Yang Liu, Jun Sun, Jing Song Dong, and Étienne André |
Automatic Compositional Verification of Timed Systems |
FM 2012, 2012 |
C |
|
|
RT |
|
|
TA |
| Charles Lakos and Laure Petrucci |
Modular State Space Exploration for Timed Petri Nets |
Journal of Software Tools for Technology Transfer(9):3-4, pages 393-411, 2007 |
|
M |
PN |
|
|
|
|
| Charles Lakos and Laure Petrucci |
Modular state spaces for prioritised Petri nets |
Monterey 2010, 2010 |
|
M |
PN |
|
|
|
|
| Truong Khanh Nguyen, Jun Sun, Yang Liu, and Jin Song Dong |
Symbolic Model-Checking of Stateful Timed CSP Using BDD and Digitization |
ICFEM 2012, 2012 |
|
|
|
RT |
|
|
TA |
| Truong Khanh Nguyen, Jun Sun, Yang Liu, Jin Song Dong, and Yan Liu |
Improved BDD-Based Discrete Analysis of Timed Systems |
FM 2012, 2012 |
|
|
|
RT |
|
|
TA |
