Itanium: Architecture, compilation techniques and multi-processor systems
Speakers and Affiliation:
J.F. Collard and Stephane Eranian, Hewlett-Packard Laboratories
This tutorial presents the Itanium family of processors, including the instruction set, specific compilation
techniques, performance monitors, and multiprocessor architecture.
The first part will introduce the instruction set of the Itanium architecture, including instruction
predication, groups of parallel instructions, counted and pipelined loops, data and control
speculation, prefetching, rotating registers, and more. The goal this part is to make the attendees
comfortable reading and writing simple Itanium assembly code. Advanced topics will be addressed,
including software pipelining using rotating registers.
In the second part, Performance monitors, which report how
cycles are spent and in which instructions, will be
presented. Some micro-architectural issues will also be
discussed, including cache issues and dispersal of
instruction in parallel groups to functional units. Recent
developments, such as HP's dual core Hondo modules, will also be detailed.
In the third part, multiprocessor architecture will be discussed, including memory consistency and
synchronization mechanisms on Itanium processors. The architecture of commercial systems will be
detailed, which, as of mid-June 2004, scale up to 128 Itanium cores.
About the Speakers:
Jean-Francois Collard got a Ph.D. in 1995 from the University of Paris 6. He was a researcher at the
French National Center for Scientific Research from 95 to 2000, when he joined the Intel Itanium
compiler team in Santa Clara, Califonia. In 2003, he joined the Hewlett-Packard Laboratories in
Palo Alto. He is part of the Advanced System Architecture Research Department led by Norm
Stephane Eranian is a senior research scientist at Hewlett
Packard Labs where he has been working on the port of Linux
to the IA-64 platform since 1998. He has made numerous
contributions to the Linux/ia64 kernel and related user level
programs. He is the main architect of the Linux/ia64 kernel
performance monitoring subsystem (perfmon). He is also the
creator of the pfmon tool which uses this subsystem to
collect performance information.
Before joining HP, Stephane was working on his Ph.d at Chorus
Systems (now Jaluna) in France. He holds a D.E.A. (B.Sc
degree) in Operating systems from Universite PARIS 6, France
and a Doctorate (Ph.D degree) in Computer Science from
Universite PARIS 7, France. He is a member of USENIX and
co-author of the book "IA-64 Linux kernel: design and implementation".