PACT'04 ADVANCE PROGRAM

(Last update: Friday 17, 2004 - 19:13)

Organization at a glance:


Workshops:

September 29, 2004

Room 1

Room 2

Room 3

Room 4



AM

HiPEAC Steering committee

MEDEA workshop

Tutorial 1: Exploitation of Locality and Parallelism in Pointer-based Programs - Oscar Plata and Rafael Asenjo, University of Malaga, Spain

Meeting of french PhD students in parallel architecture and compilation. Student may click here for more information in French and how to register.

PM

HiPEAC Steering committee

Tutorial 2: Itanium: Architecture, compilation techniques and multi-processor systems – Jean François Collard and Stéphane Eranian, Hewlett-Packard Laboratories


Meeting of french PhD students in parallel architecture and compilation. Student may click here for more information in French and how to register.



September 30, 2004

Room 1

Room 2

Room 3

Room 4



AM


AGRID workshop

SNAPI workshop

Meeting of HiPEAC network of excelence

PM


Tutorial 3: UPC: Unified Parallel C - Tarek El-Ghazawi, The George Washington University

SNAPI workshop

Meeting of HiPEAC network of excelence

18:00

REGISTRATION and WINE TASTE



Conference:


Friday, October 1st



08:45

Chair: Mateo Valero

Keynote Speech: Wen-Mei Hwu, University of Illinois at Urbana Champaign, USA.

Title: Breaking Down the Memory Wall for Scalable Microprocessor Platforms. Download his presentation.

10:00


Break

10:30

Session 1: Code Generation

Chair: Mike O'Boyle

Code Generation in the Polyhedral Model Is Easier Than You Think

Cédric Bastoul – PriSM (Versailles)


A Compiler Framework for Recovery Code Generation in General Speculative Optimizations

Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook. Ngai - University of Minnesota


A Portable, Multiplatform, High-Performance Co-Array Fortran Compiler.

Yuri Dotsenko, Cristian Coarfa, John Mellor-Crummey - Rice University


Retargeting JIT compilers by using C-compiler generated executable code

M. Anton Ertl and David Gregg - TU Wien

12:30


Lunch

14:00

Session 2: Architecture

Chair: Toshinori Sato

Adding Limited Reconfigurability to Superscalar Processors

Marc Epalza, Paolo Ienne, Daniel Mlynek - EPFL


Architectural Support for Enhanced SMT Thread Scheduling

Alex Settle, Joshua Kihm, Andrew Janiszewski, Dan Connors - University of Colorado


Instruction Scheduling for Static Issue, Dynamic Placement (SPDI) Architectures

Ramadass Nagarajan, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler - University of Texas at Austin


A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design

Gheorghe Almasi, Leonardo Bachega, Luiz H. Ceze, Siddharth Chatterjee, Kenneth A. Dockser, Maria Eleftheriou, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Karin Strauss - IBM (T.J. Watson)

16:00


Break

16:30 – 18:00

Session 3: Parallel Systems

Chair: Jakob Engblom


Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization

Jialin Dou and Marcelo Cintra - University of Edinburgh


Implementing Malleability on MPI jobs

Gladys Utrera, Julita Corbaln, Jess Labarta - Universidad Politcnica de Catalua


Partitioning of Code for a Massively Parallel Machine

Michael Ball, Cristina Cifuentes and Deepankar Bairagi - Sun Microsystems



Banquet at « Keller Plage »



Saturday, October 2nd



09:00

Chair: Josep Lluis Larriba-Pey

Keynote Speech: Tadashi Watanabe, NEC, Japan

Title: "The Earth Simulator and its Beyond - Technological Considerations towards the Sustained PetaFlops Machine -"

10:00


Break

10:30

Session 4: Memory Hierarchy

Chair: Avi Mendelson

Impact of Java Memory Model on Out-of-order Multiprocessors

Tulika Mitra, Abhik Roychoudhury, Qinghua Shen - National University of Singapore


Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture

Seongbeom Kim, Dhruba Chandra, Yan Solihin - North Carolina State University


Architecture Support for High Speed Authentication of Shared Memory in Multi-processor System

Weidong Shi, Hsien-Hsin Sean Lee, Mrinmoy Ghosh, Chenghuai Lu - Georgia Institute of Technology


AC/DC: Adaptive CZone / Delta Correlation Prefetcher

Kyle J. Nesbit, Ashutosh S. Dhodapkar, James E. Smith - University of Wisconsin - Madison

12:30


Lunch

14:00 – 16:00

Session 5: Compiler optimizations

Chair: Jesse Fang

The Energy Impact of Aggressive Loop Fusion

Y. Zhu and G. Magklis and M. L. Scott and C. Ding and D. H. Albonesi - University of Rochester


Scalable High Performance Cross-Module Inlining

Dhruva R. Chakrabarti, Luis A. Lozano, Xinliang D. Li, Robert Hundt, Shin-Ming Liu - HP


Decoupled Software Pipelining with the Synchronization Array for Latency Tolerance

Ram Rangan, Neil Vachharajani, David August - Princeton University


Fast Paths in Concurrent Programs

Wen Xu, Sanjeev Kumar, and Kai Li - Princeton University & Intel Corporation



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Sunday, October 3rd



09:00

Chair: Michel Cosnard

Keynote Speech: Stamatis Vassiliadis, T.U. Delft, The Nederlands

Title: Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers. Download his presentation.

10:00


Break

10:30

Session 6: Memory Parallelism

Chair: Pedro Trancoso

The Value Evolution Graph and its Use in Memory Reference Analysis

Silvius Rus, Dongmin Zhang, and Lawrence Rauchwerger - Texas A&M University


TO-lock: Removing Lock Overhead Using the Owners' Temporal Locality

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Takeshi Ogasawara, Hideaki Komatsu, and Toshio Nakatani - IBM Research


The Stream Virtual Machine

François Labonte, Ian Buck, Bill Thies, Peter Mattson, Christos Kozyrakis, Mark Horowitz - Stanford University


An » Adaptive Algorithm Selection Framework

Hao Yu, Dongmin Zhang, Francis Dang, Lawrence Rauchwerger - Texas A&M University

12:30


Concluding Remarks